ICD In-Circuit Debugger
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ICD In-Circuit Debugger

Picture
  Highlights
Easy high-level and assembler debugging
Interface to all compilers
RTOS awareness
Interface to all hosts
Fast download
Display of internal and external peripherals at a logical level
Flash programming
Hardware breakpoints and trigger (if supported by on chip debug interface)
Multiprocessor/multicore debugging
Trace and trigger extension possible
Software trace
Virtual analyzer
Software compatible to all TRACE32 tools
 
  Introduction
TRACE32-ICD are microprocessor development tools based on the debug and trace logic (BDM, JTAG, ETM, OCDS, NEXUS) integrated on the chip. On this basis TRACE32-ICD provides a highly cost effective debugger plus a powerful trace and run time analysis tool.

TRACE32-ICD can be connected to the host by an ethernet, USB or LPT interface.


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TOP       Basic Concept

The TRACE32 In-Circuit Debuggers are highly cost effective tools for debugging on assembler or HLL level. The ICD-Debugger are mainly used as stand-alone debugger on a PC or workstation. But they are also offered as an extension to the In-Circuit Emulator TRACE32-ICE using the PODBUS connector on the ECU32. In this configuration they can be used to debug a second CPU on the target.

Debugger Configurations

The ICD-Debugger is based on the on-chip debug interface (e.g. BDM, ONCE, JTAG etc.). TRACE32-ICD supports all extra features offered by on-chip debug interface like hardware breakpoints or trigger capabilities. An optional EPROM/FLASH Simulator is provided to allow the settting of breakpoints in the ROM area.


    PowerDebug BDM/JTAG Debugger with RISC Controller and USB Interface


    PowerDebug BDM/JTAG Debugger with RISC Controller and USB/Ethernet Interface


    PowerDebug II BDM/JTAG Debugger with RISC Controller and USB/Ethernet Interface

Integrated Debugger/Trace Configurations

For microcontrollers with NEXUS port an integrated Debugger/Trace/Performance-Analyzer System is on development.



    PowerNexus NEXUS Debugger


    PowerTrace BDM/JTAG Debugger with RISC Controller, Trace and USB/Ethernet Interface



    PowerTrace BDM/JTAG Debugger with RISC Controller, Trace and USB/Ethernet Interface

ROM Monitor Configuration

The ICD-Debugger is based on a ROM Monitor solution. An 8KB monitor program may be located anywhere in the address space. The monitor can be linked and loaded separatly or ist can be linked and loaded along with the user program. To implement the monitor, some interrupt vectors must be reserved for the monitor program use and these must be allowed for in the target software design.
The communication between the Debugger on the host and the monitor program is done using an EPROM/FLASH simulator. The EPROM simulator can support two 8-bit or one 16-bit EPROM. The combination of several modules allows 32- or 64-bit configurations to be supported. During the simulation the EPROM configuration of the target system can be imitated by the software in the EPROM simulator. Using this technique paged or banked EPROM壮 can be simulated. For more information on the EPROM simulator refer to its documentation.


    EPROM/FLASH Simulator

PowerProbe Logic and Protocol Analyzer

The state/timing analyzer module is a full 64 channel logic analyzer module. It is connected via the POD-Bus.


    PowerProbe Logic Analyzer

PowerIntegrator Logic Analyzer

The state/timing analyzer logic analyzer is especially designed for system integration. It is connected via the POD-Bus.


    PowerIntegrator Logic Analyzer with MICTOR probes

Stimuli Generator

The Stimuli Generator is a extension the TRACE32-ICD In-Circuit Debuggers. 64 digital and 12 analog channels are available.


    Stimuli Generator

Trigger Probe

The trigger probe enables the usage of external trigger events in an in-circuit debugger system.


    Trigger Probe

Clip Set


    Clip Set

PowerSupply


    Power Supply

Multiprocessor Debugging

One PODBUS can controll up to 4 independent devices. Each device or each combination of devices is controlled by a different user interface. The TRACE32 software allows to start and stop multiple devices synchronously to offer multiprocessor debugging. Using this configuration e.g. one master can controll up to 3 slaves.




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ICD Tutorial

TOP       Modules



     EPROM/FLASH Simulator

8, 16 or 32 Bit Operation
2, 8, 16 or 64 MBit Versions
DIL or PLCC Adapters
SO Adapter
TSOP Adapter
ESI-CON for In-Circuit Simulation
Monitor Control
NMI and RESET Generation

     ROM Monitor

Compatible with Emulator
Support for C,C++ and ASM
Communication via Eprom Simulator
Communication via RS232 or customized .DLL link
Windows9x, WindowsNT and Unix
Monitor Code with Source
Monitor Code Royalty Free






     JTAG Debugger

Support for a wide range of on-chip debug interfaces
Easy high-level and assembler debugging
Interface to all compilers
Fast download
RTOS awareness
Interface to all hosts
Display of internal and external peripherals
at a logical level
Flash programming
Hardware breakpoints and trigger (if supported by chip)
Trace extension available
Multiprocessor/multicore debugging
Software trace
Virtual analyzer
USB, Ethernet or Parallel Interface

     PowerTrace for NEXUS

Support for NEXUS standard class 1 to 3+
Programming support for on-chip and external flashes
Real-time access to memory
Hardware breakpoints and trigger
Program and data flow trace up to 400 MHz
Up to 4 GByte trace memory
Upload to host within 10 seconds typically
Selective data flow trace for 2 address ranges
Trigger on instruction execution or data access
Statistic functions/Performance analysis
Code coverage
External trigger input and output
USB and ETHERNET interface included

     Stimuli Generator

64 Digital Channels
12 Analog Channels
Pulse Generator
Pattern Generator
Connection Tester

     Trigger Probe for PODBUS

Works with ICE, FIRE and ICD
Asynchronous Trigger
Synchrounous Trigger
Pulse Width Trigger
Glitch Trigger
Scope Trigger Output

     PowerTrace

Fast debugger and very fast download
Upload of full trace within 10 seconds
Programming support for on-chip and external flashes
Hardware breakpoints and trigger (if supported
by the on-chip debugging support)
Program and data flow trace
256 or 512 MByte trace memory
300 MHz effective sample rate with AUTOFOCUS
self calibration
Statistic functions
Performance analysis
Code Coverage
USB and Ethernet interface included


     PowerTrace-II

High speed Real Time Trace
Upload and full processing within 30 seconds
per Gigabyte trace storage
Hardware breakpoints and trigger (if supported
by the on-chip debugging unit)
Program and data flow trace
1, 2 or 4 GByte trace memory
500+ MHz effective sample rate with AUTOFOCUS-II
self calibration
16 GBit/s total trace port bandwidth
Statistic functions
Performance analysis
Code Coverage
Energy Tests (with optional Analog Probe)
17 logic analyzer channels
PodBusExpress interface to PowerDebug II (Host
interface of PowerDebug II: USB2 and Ethernet 10/100/1000)

     PowerProbe

Timing Analyzer up to 400 MHz
State Analyzer up to 100 MHz
64 Input Channels
Transient Recording
Time Correlation with RISC Trace
Clock Qualifier for State Clock
Mixed State and Timing Mode
4 State Clock Inputs
Optional FPGA Onchip Trace
Optional Pattern Generator
Protocol Support for CAN, USB, etc.

     PowerIntegrator

Timing Analyzer with 500 MHz on all Channels
State Analyzer up to 200 MHz DDR
204 Input Channels
Transient Recording
Time Correlation with other Tracetools
Clock Qualifier for State Clock
Mixed State and Timing Mode
4 Clock Inputs
MICTOR and Standard Probes (single ended)
MICTOR differential Probes
Analog Voltage and Current Probe
3G/DigRF Protocol Support


TOP       Configuration Examples

TOP       Debugger Module and EPROM/FLASH Simulator on PC with USB Interface

 
BDM/JTAG Debugger
with USB Interface
EPROM/FLASH Simulator Module
 
TOP       PowerTrace on PC or Workstation

Hub
PowerTrace BDM/JTAG Debugger and Trace
 
TOP       PowerTrace and Logic Analyzer on PC or Workstationr

Hub
PowerTrace BDM/JTAG Debugger and Trace
PowerProbe 400 MHz Logic Analyzer
 






Copyright © 2010 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: 2-Sep-2010